Many digital logic circuits have a modular design comprising a plurality of logic circuit blocks each implemented in hardware (HW). A logic circuit block may be designed using a hardware description language such as VHDL or Verilog. A logic circuit block typically has an interface for control data and an interface for data access. In addition to that, one or several specific interfaces may exist for direct access to other logic circuit blocks, external interfaces or processing blocks adapted to execute software (SW), like CPUs, DSPs or sequencers. For the purpose of the present description, a logic circuit block of a digital logic circuit implemented in hardware will also be referred to as a HW block.
The configuration of a logic circuit block is normally done by software running on a CPU, DSP, Sequencer or similar processing unit. The configuration parameters are sent to the logic circuit block on the control interface. When the configuration of the logic circuit block is finished it is started by software and executes either continuously or until done, depending on the function that the logic circuit block implements. When the logic circuit block is done, it may inform the software entity by sending an interrupt or by writing to a status bit that can be read by SW.
Hence, the HW block normally needs to be configured and started by SW, and when a HW block is done it needs to signal to the SW that it is done using an interrupt, a SW polling mechanism, or another method. This results in the SW receiving a high interrupt load and/or in the need for polling of HW block status registers by SW and/or that the SW has a good timing understanding of the system, e.g. knowing when the HW blocks are done and when the result from one HW block can be used by SW or by another HW block.
In real-time systems such as communications devices, it can be difficult for the SW entity to perform the programming of the HW entities at the correct time, which often leads to over-dimensioning of HW entities, SW entities and/or interface HW when it comes to performance to secure that the real time constraints in the system are not broken.
WO 2008/014493 shows an accelerator module referred to as a reconfigurable processor unit (RPU), which may be coupled to a motherboard. The RPU may access system memory that is also accessible by a microprocessor. The RPU includes an FPGA in which a user available programmable logic fabric may be coupled via a wrapper interface to memories external to the FPGA. The FPGA can be re-programmed by having one or several bit streams for doing the re-programming stored in memory and a controller for controlling the actual reconfiguration.
It is thus generally desirable to provide HW blocks that reduce the interrupt intensity of a system comprising such HW blocks.
It is further generally desirable to provide HW blocks that are easily (re-)configurable.
It is further generally desirable to provide HW blocks that are power efficient.